1. Technical Field
The present invention relates to a method of manufacturing a semiconductor device.
2. Related Art
A problem of delay of the propagation of signals flowing on a wiring may occur with a miniaturization of large scale integration (LSI) devices. Therefore, in the devices emerged after 28 nm or 32 nm technology, use of a porous SiCOH film (hereinafter, referred to as a “p-SiCOH film”) having k (dielectric constant) equal to or less than 2.5 (k≦2.5) is taken into consideration.
The related art includes techniques disclosed in Japanese laid-open patent publication NO. 2006-041519.
The present inventor has recognized as follows. The problems with the method of manufacturing a semiconductor device will be described with reference to FIGS. 3A to 3L, with an example of a Via-First Dual Damascene process using a p-SiCOH film (where k=2.4). Moreover, the same problems also may occur even when a Trench-First technique is used.
As shown in FIG. 3A, a first Cu wiring 102 is formed using a first p-SiCOH film 101 as an interlayer insulating film, and then a SiCN film 103 and a second p-SiCOH film 104 are sequentially laminated on the first Cu wiring 102.
Next, as shown in FIG. 3B, a SiO2 film 106 serving as a hard mask is formed on the second p-SiCOH film 104. At this time, tetraethoxysilane (TEOS) or O2 is sometimes used as a film forming gas for the SiO2 film 106. In this case, since oxygen is contained in the film forming gas, after the SiO2 film 106 is formed, a damaged layer 105 is produced in a portion of the second p-SiCOH film 104 being in contact with the SiO2 film 106.
Next, as shown in FIG. 3C, a first lower resist layer 107, an anti-reflection film 108, and a first upper resist layer 109 are sequentially formed on the SiO2 film 106, and then the first upper resist layer 109 is patterned into a via pattern by exposure and development. Thereafter, the anti-reflection film 108, the first lower resist layer 107, the SiO2 film 106, and the second p-SiCOH film 104 are etched using the patterned first upper resist layer 109 as a mask to form an opening serving as a via. At this time, part of the damaged layer 105 is also removed. The first upper resist layer 109 and the anti-reflection film 108 masked with the first upper resist layer 109 are also removed. Then, the remaining first lower resist layer 107 is removed by plasma asking and a structure shown in FIG. 3D can be obtained. At this time, a damaged layer 110 is formed on the sidewall of the opening, that is, on the exposed surface of the second p-SiCOH film 104.
Next, as shown in FIG. 3E, a second lower resist layer 111 is formed on the SiO2 film 106 to bury the opening serving as a via. Then, a low-temperature oxide (LTO) film 112, a second anti-reflection film 119, and a second upper resist layer 113 are sequentially formed on the second lower resist layer 111, and then the second upper resist layer 113 is patterned into a trench pattern serving as a wiring by exposure and development. Thereafter, by using the patterned second upper resist layer 113 as a mask, the second anti-reflection film 119, the LTO film 112, the second lower resist layer 111, the SiO2 film 106, and the second p-SiCOH film 104 are etched up to about 50% of the depth of the second p-SiCOH film 104. At this time, parts of the damaged layers 105 and 110 are also removed. Moreover, the second upper resist layer 113, the second anti-reflection film 119 masked with the second upper resist layer 113, and the LTO film 112 are also removed. Then, the remaining second lower resist layer 111 is removed by plasma ashing and a structure shown in FIG. 3F can be obtained. At this time, the damaged layer 110 is formed on the sidewall of the opening, that is, on the exposed surface of the second p-SiCOH film 104.
Thereafter, the opening formed through the above process is buried with metal to form the via hole and the wiring. However, when the opening is buried with the metal in a state where the damaged layer 110 formed on the sidewall of the opening remains, a dielectric constant increases and thus a problem occurs in that a desired inter-wiring capacitance may not be obtained. Accordingly, it is necessary to perform a process of removing the damaged layer 110 by pre-treatment of the burying of the metal. This process is performed with a cleaning liquid, such as diluted-HF (DHF), containing hydrofluoric acid. Since the damaged layer 110 on the sidewall of the opening can be removed in this process, a structure shown in FIG. 3H can be obtained.
In the structure shown in FIG. 3H, step portions are formed between the SiO2 film 106 and the underlying layer thereof due to an etching rate difference (the etching rate of the damage layer 110 is much higher than that of the SiO2 film 106) between the SiO2 film 106 and the damaged layer 110 in the cleaning process. That is, overhang portions A are formed by the SiO2 film 106. When such overhang portions A are formed, the following problems may occur in the subsequent processes.
First, as shown in FIG. 3H, a barrier metal 114 is formed along the sidewall of the opening after the damaged layer 110 is removed. However, when there are the overhang portions A, as shown in FIG. 3I, a problem may arise in that the barrier metal 114 may not be sufficiently formed near the overhang portions A.
By forming Cu seed through a sputtering method after the formation of the barrier metal 114 and then forming a Cu-plated film by a plating method, a Cu film 115 is formed to fill the opening. However, when there are the overhang portions A, as shown in FIG. 3J, a problem may arise in that the opening may not be completely filled with the Cu film 115 and a void 116 may be generated. Moreover, it is considered that the void 116 is generated due to the high aspect ratio of the opening.
A problem may arise in that Cu may be released toward the SiO2 film 106 and the second p-SiCOH film 104, and thus a Cu-escaped portion 117 may be generated after the heat treatment of the Cu plating (see FIG. 3K).
As a consequence, a chemical mechanical polishing (CMP) treatment is performed, and then a slit 118 may be formed due to the void 116, as shown in FIG. 3L. Moreover, a problem that the Cu-escaped portion 117 remains may arise.
In order to resolve the above-mentioned problems, use of a process of removing the SiO2 film 106 (hard mask) before the metal is buried in the opening may be taken into consideration. According to this process, the removal of the overhang portions A and improvement in the aspect ratio of the opening can be realized.
However, the inventors have found that a new problem occurs. When the damaged layer 105 is produced in the portion of the second p-SiCOH film 104 being in contact with the SiO2 film 106, as described above, the exposed surface becomes uneven after the removal of the SiO2 film 106 and thus the surface area increases. That is, a structure in which the second p-SiCOH film 104 easily absorbs moisture in the air may be formed. In this case, the second p-SiCOH film 104 absorbs much moisture (moisture or the like in the air) when the SiO2 film 106 is removed in the early stage of the manufacturing procedure.
Also the inventors have found that in the above method of manufacturing a semiconductor device, other following problems may occur.
That is, in the process of cleaning the inside of the opening after the structure in FIG. 3H is obtained, partially or entirely the damage layer 105 formed in the contact portion of the second p-SiCOH film 104, the portion being in contact with the SiO2 film 106, may be removed (see FIG. 3G).
In this case, partially or entirely the SiO2 film 106 is removed by lift-off. As a consequence, a problem may arise in that the second p-SiCOH film 104 absorbs much of the cleaning liquid due to an increase in the surface area of the second p-SiCOH film 104 being in contact with the cleaning liquid. Moreover, a problem may arise in that the removed SiO2 film 106 is attached to an unintended portion on the semiconductor device.